搜索资源列表
i2c_AT24C04_Verilog
- 用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
edaok_UART_FPGA
- 用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
uart
- 采用verilog语言描述的uart串口驱动程序主要用于调试-Using verilog language to describe the uart serial port driver is mainly used for debugging
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
uart.v.tar
- uart Universal asyncronous receiver and transmitter verilog code
uart
- 基于verilog HDL编写的串口通讯接口uart程序-Prepared based on verilog HDL uart serial communication interface program
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
RS-232C_UART
- 基于Verilog的RS-232C（UART）接口的设计与实现 -Based on Verilog' s RS-232C (UART) interface, Design and Implementation
uart
- verilog实现的按键控制的串口简单收发通信-verilog implementation simple keypad control, serial communication transceiver
send
- 串口发送子程序verilog 串口发送子程序verilog -uart send verilog
Uart
- 用Verilog编写的实现UART接口的源程序-Prepared with the Verilog source code to achieve UART interface
uart_control
- 用verilog 实现的简易串口驱动模块儿，引脚简单，易用，可自己增减配置-verilog uart
veriloguart
- 简易的串口模块儿驱动程序，用verilog语言描述，自己可以进行增加或裁剪-verilog uart
UART
- verilog hdl UART de bo xing-verilog
sdram
- 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xx